| PART |
Description |
Maker |
| CBRLDSH2-40 CBRLDSH2-40-15 |
SURFACE MOUNT HIGH DENSITY HIGH DENSITY SCHOTTKY BRIDGE RECTIFIER
|
Central Semiconductor C...
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| ISPLSI2032VL-135LT44I ISPLSI2096VL ISPLSI2096VL-10 |
2.5VIn-SystemProgrammableSuperFASTHighDensityPLD
2.5V In-System Programmable SuperFAST⑩ High Density PLD
2.5V In-System Programmable SuperFAST High Density PLD
2.5V In-System Programmable SuperFASTHigh Density PLD EE PLD, 8 ns, PQFP128
2.5V In-System Programmable SuperFASTHigh Density PLD EE PLD, 10 ns, PQFP44
|
LATTICE[Lattice Semiconductor]
LATTICE [Lattice Semiconductor]
Lattice Semiconductor Corporation
Lattice Semiconductor, Corp.
|
| ISPLSI2128E-100LT176 ISPLSI2128E-135LT176 ISPLSI21 |
In-SystemProgrammableSuperFASTHighDensityPLD
In-System Programmable SuperFASTHigh Density PLD EE PLD, 7.5 ns, PQFP176
In-System Programmable SuperFAST High Density PLD
In-System Programmable SuperFAST⑩ High Density PLD
In-System Programmable SuperFAST?/a> High Density PLD
|
Lattice Semiconductor, Corp.
Lattice Semiconductor Corporation
LATTICE[Lattice Semiconductor]
|
| WP06R WP06R12D05 WP06R12D12 WP06R12D15 WP06R12S05 |
High Density 5-6 Watt Wide Input Range DC/DC Converter
5-6 WATT HIGH DENSITY, WIDE INPUT RANGE DC/DC CONVERTER
5-6 WATT HIGH DENSITY/ WIDE INPUT RANGE DC/DC CONVERTER
RECTIFIER SCHOTTKY SINGLE 2A 40V 50A-Ifsm 0.55Vf 0.5A-IR PowerDI-123 3K/REEL
|
CANDD[C&D Technologies]
|
| ISPLSI2192VL-100LB144 ISPLSI2192VL-100LT128 ISPLSI |
2.5V In-System Programmable SuperFAST High Density PLD
TRIAC STANDARD 12A 400V TO-220AB
2.5V In-System Programmable SuperFASTHigh Density PLD
|
Lattice Semiconductor Corporation
|
| DK50-1.0 DK50-1.0M DK44-1.0 DK44-1.0M DK60-1.0 DK6 |
1.0mm High Density FLEX (300V, 105隆?C)
1.0mm High Density FLEX (300V, 105掳C)
1.0mm High Density FLEX (300V, 105°C)
|
Yamaichi Electronics Co., Ltd.
http://
|
| LTV8192M LTV-819-1S-TA LTV829S-V LTV-829S-TA LTV82 |
High Density Mounting Type Photocoupler 1 CHANNEL TRANSISTOR OUTPUT OPTOCOUPLER
High Density Mounting Type Photocoupler 2 CHANNEL TRANSISTOR OUTPUT OPTOCOUPLER
High Density Mounting Type Photocoupler(762.22 k) 高密度安装类型光电耦合62.22十一
|
Lite-On Technology, Corp.
|
| ISOPAC01 ISOPAC0103 ISOPAC0104 ISOPAC0111 ISOPAC01 |
High Current High density Isolated Silicon Power Rectifier(????靛?600V锛?ぇ?垫?锛??瀵?害锛??绂诲?锛??????存???
High Current High density Isolated Silicon Power Rectifier(????靛?1000V锛?ぇ?垫?锛??瀵?害锛??绂诲?纭?????娴??)
High-Current Isolated Rectifier Assemblies. 150 V-1000 V. 10 nS - 2 microseconds 大电流隔离整流器大会150 V000五，10纳秒- 2微秒
HIGH CURRENT ISOLATED RECTIFIER ASSEMBLY
High Current High density Isolated Silicon Power Rectifier(????靛?1000V锛?ぇ?垫?锛??瀵?害锛??绂诲?锛??????存???
|
International Rectifier, Corp.
Semtech Corporation
|
| EDI3DG328V8D1 EDI3DG328V10D1 |
8Megx32 Synchronous High Density DRAM Modules 3.3V(125MHz,3.3V,8M x32同步高密度动态RAM模块)
8Megx32 Synchronous High Density DRAM Modules 3.3V(100MHz,3.3V,8M x32同步高密度动态RAM模块) 8Megx32同步高密度DRAM模块3.300MHz的，3.3分X32号，同步高密度动态内存模块）
|
Bourns, Inc.
|
| M38230G4-XXXFP M38230G4-XXXHP M38231G4-XXXHP M3823 |
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 512Kb x 36; Vcc (V): 3.1 to 3.6 V
36-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 2.4 to 2.6 V
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 3.1 to 3.6 V
18-Mbit (512K x 36/1M x 18) Pipelined SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V
72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V
36-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2 M x 18/512K x 72) Flow-Through SRAM with NoBL(TM) Architecture; Architecture: NoBL, Flow-through; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 1Mb x 72; Vcc (V): 2.4 to 2.6 V
72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 3.1 to 3.6 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 512Kb x 72; Vcc (V): 3.1 to 3.6 V
72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
Sync SRAM; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 2.4 to 2.6 V
72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 1Mb x 72; Vcc (V): 3.1 to 3.6 V
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V
72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency); Architecture: QDR-II , 4 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
72-Mbit DDR-II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency); Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V 单芯位CMOS微机
72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V 单芯位CMOS微机
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 单芯位CMOS微机
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 2.4 to 2.6 V 单芯位CMOS微机
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V 单芯位CMOS微机
72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
36-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 单芯8位CMOS微机
Sync SRAM; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
|
Renesas Electronics Corporation.
Renesas Electronics, Corp.
|
| ISPLSI5256VE-125LT100I ISPLSI5256VE-100LF256I ISPL |
In-system programmable 3.3V SuperWIDE high density PLD. fmax 80 MHz, tpd 12 ns.
EE PLD, 10 ns, PBGA256
In-system programmable 3.3V SuperWIDE high density PLD. fmax 100 MHz, tpd 10 ns.
In-system programmable 3.3V SuperWIDE high density PLD. fmax 125 MHz, tpd 7.5 ns.
In-system programmable 3.3V SuperWIDE high density PLD. fmax 165 MHz, tpd 6.0 ns.
|
Lattice Semiconductor, Corp.
LATTICE SEMICONDUCTOR CORP
|
